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? semiconductor components industries, llc, 2008 august, 2008 ? rev. 3 1 publication order number: NCP5392/d NCP5392 2/3/4-phase controller for cpu applications the NCP5392 provides up to a four ? phase buck solution which combines differential voltage sensing, differential phase current sensing, and adaptive voltage positioning to provide accurately regulated power for both intel and amd processors. dual ? edge pulse ? width modulation (pwm) combined with inductor current sensing reduces system cost by providing the fastest initial response to dynamic load events. dual ? edge multiphase modulation reduces the total bulk and ceramic output capacitance required to meet transient regulation specifications. a high performance operational error amplifier is provided to simplify compensation of the system. dynamic reference injection further simplifies loop compensation by eliminating the need to compromise between closed ? loop transient response and dynamic vid performance. features ? meets intel?s vr11.1 specifications ? meets amd 6 bit code specifications ? dual ? edge pwm for fastest initial response to transient loading ? high performance operational error amplifier ? internal soft start ? dynamic reference injection ? (patent #us07057381) ? dac range from 0.375 v to 1.6 v ? dac feed forward (patent pending) ? 0.5% dac voltage accuracy from 1.0 v to 1.6 v ? true differential remote voltage sensing amplifier ? phase ? to ? phase current balancing ? ?lossless? differential inductor current sensing ? differential current sense amplifiers for each phase ? adaptive voltage positioning (avp) ? oscillator frequency range of 100 khz ? 1 mhz ? latched over voltage protection (ovp) ? guaranteed startup into pre ? charged loads ? threshold sensitive enable pin for vtt sensing ? power good output with internal delays ? thermally compensated current monitoring ? this is a pb ? free device applications ? desktop processors 40 pin qfn, 6x6 mn suffix case 488ar device package shipping ? ordering information NCP5392mnr2g* qfn ? 40 (pb ? free) 2500/t ape & reel marking diagram NCP5392 = specific device code a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package NCP5392 awlyywwg 1 http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. *pin 41 is the thermal pad on the bottom of the device. *temperature range: 0 c to 85 c 40 1
NCP5392 http://onsemi.com 2 g1 30 drvon 29 cs4 28 cs4n 27 cs3 26 cs3n 25 cs2 24 cs2n 23 cs1 22 cs1n 21 vr_hot 40 vr_rdy 39 ntc 38 psi 37 dac 36 vcc 35 12vmon 34 g4 33 g3 32 g2 31 en 1 vid0 2 vid1 3 vid2 4 vid3 5 vid4 6 vid5 7 vid6 8 vid7 9 rosc 10 ilim 11 imon 12 vsp 13 vsn 14 diffout 15 comp 16 vfb 17 vdrp 18 vdfb 19 cssum 20 NCP5392 pin connections 2/3/4 ? phase buck controller (qfn40) figure 1. NCP5392 qfn40 pin connections (top view)
NCP5392 http://onsemi.com 3 g1 + ? g2 g3 overvoltage protection + ? g4 control, fault logic and monitor circuits imon drvon psi ntc vr_hot vr_rdy uvlo ilimit 4.25 v + ? + ? + ? + ? + rosc cs4n cs4p cs3n cs3p gnd (flag) cs2n cs2p cs1n cs1p cssum vdfb vdrp comp vfb diffout vsp vsn vid7/amd vid6 vid5 vid4 vid3 vid2 vid1 vid0 flexible dac droop amp error amp + ? diff amp + ? 1.3 v + ? + + + oscillator gain = 6 + ? gain = 6 gain = 6 gain = 6 + ? + ? + ? + ilim en vcc dac figure 2. NCP5392 block diagram + + + + ? 12vmon ? 2/3
NCP5392 http://onsemi.com 4 cpu gnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd rt1 rntc1 imon psi ntc imon 38 12 psi vcc 12vmon 37 35 34 12v_filter +5v vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vtt 2 3 4 5 6 7 8 9 1 39 40 14 13 15 16 17 18 19 20 36 en vr_rdy vr_hot vsn vsp diffout comp vfb vdrp vdfb cssum dac gnd ilim rosc 41 11 10 rlim1 rlim2 riso1 riso2 rt2 cdfb rnor r6 r6 cdni rdnp ch rf rfb1 rfb cf cfb1 rdrp 30 22 21 31 24 23 32 26 25 33 28 27 29 g1 cs1p cs1n g2 cs2p cs2n g3 cs3p cs3n g4 cs4p cs4n drvon vccp vssn figure 3. application schematic for four phases NCP5392 + q1 q2 r2 rs1 cs1 c2 c4 c3 d1 c1 l1
NCP5392 http://onsemi.com 5 cpu gnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd rt1 rntc1 imon psi ntc imon 38 12 psi vcc 12vmon 37 35 34 12v_filter +5v vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vtt 2 3 4 5 6 7 8 9 1 39 40 14 13 15 16 17 18 19 20 36 en vr_rdy vr_hot vsn vsp diffout comp vfb vdrp vdfb cssum dac gnd ilim rosc 41 11 10 rlim1 rlim2 riso1 riso2 rt2 cdfb rnor r6 r6 cdni rdnp ch rf rfb1 rfb cf cfb1 rdrp 30 22 21 31 24 23 32 26 25 33 28 27 29 g1 cs1p cs1n g2 cs2p cs2n g3 cs3p cs3n g4 cs4p cs4n drvon vccp vssn figure 4. application schematic for three phases NCP5392 + c4 l1 rs1 r2 c2 q2 q1 d1 c3 cs1 c1
NCP5392 http://onsemi.com 6 cpu gnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd 12v_filter 12v_filter ncp5359 vcc od in bst drh sw drl pgnd rt1 rntc1 imon psi ntc imon 38 12 psi vcc 12vmon 37 35 34 12v_filter +5v vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vtt 2 3 4 5 6 7 8 9 1 39 40 14 13 15 16 17 18 19 20 36 en vr_rdy vr_hot vsn vsp diffout comp vfb vdrp vdfb cssum dac gnd ilim rosc 41 11 10 rlim1 rlim2 riso1 riso2 rt2 cdfb rnor r6 r6 cdni rdnp ch rf rfb1 rfb cf cfb1 rdrp 30 22 21 31 24 23 32 26 25 33 28 27 29 g1 cs1p cs1n g2 cs2p cs2n g3 cs3p cs3n g4 cs4p cs4n drvon vccp vssn figure 5. application schematic for two phases NCP5392 + c4 l1 rs1 r2 c2 q2 q1 d1 c3 cs1 c1
NCP5392 http://onsemi.com 7 pin descriptions pin no. symbol description 1 en threshold sensitive input. high = startup, low = shutdown. 2 vid0 voltage id dac input 3 vid1 voltage id dac input 4 vid2 voltage id dac input 5 vid3 voltage id dac input 6 vid4 voltage id dac input 7 vid5 voltage id dac input 8 vid6 voltage id dac input 9 vid7/amd voltage id dac input. pull to v cc (5 v) to enable amd 6 ? bit dac code. 10 rosc a resistance from this pin to ground programs the oscillator frequency according to f sw . this pin supplies a trimmed output voltage of 2 v. 11 ilim overcurrent shutdown threshold setting. connect this pin to the rosc pin via a resistor divider as shown in the application schematics. to disable the overcurrent feature, connect this pin directly to the rosc pin. to guarantee correct operation, this pin should only be connected to the voltage generated by the rosc pin; do not connect this pin to any externally generated voltages. 12 imon 0 mv to 900 mv analog signal proportional to the output load current. vsn referenced 13 vsp non ? inverting input to the internal differential remote sense amplifier 14 vsn inverting input to the internal differential remote sense amplifier 15 diffout output of the differential remote sense amplifier 16 comp output of the error amplifier 17 vfb compensation amplifier voltage feedback 18 vdrp voltage output signal proportional to current used for current limit and output voltage droop 19 vdfb droop amplifier voltage feedback 20 cssum inverted sum of the differential current sense inputs. av=cssum/csx = ? 4 21 cs1n inverting input to current sense amplifier #1 22 cs1 non ? inverting input to current sense amplifier #1 23 cs2n inverting input to current sense amplifier #2 24 cs2 non ? inverting input to current sense amplifier #2 25 cs3n inverting input to current sense amplifier #3 26 cs3 non ? inverting input to current sense amplifier #3 27 cs4n inverting input to current sense amplifier #4 28 cs4 non ? inverting input to current sense amplifier #4 29 drvon bidirectional gate drive enable 30 g1 pwm output pulse to gate driver. 3 ? level output: low = lsfet enabled, mid = diode emulation enabled, high = hsfet enabled 31 g2 pwm output pulse to gate driver. 3 ? level output (see g1) 32 g3 pwm output pulse to gate driver. 3 ? level output (see g1) 33 g4 pwm output pulse to gate driver. 3 ? level output (see g1) 34 12vmon monitor a 12 v input through a resistor divider. 35 vcc power for the internal control circuits. 36 dac dac feed forward output 37 psi power saving control. low = single phase operation, high = normal operation. 38 ntc threshold sensitive input for thermal monitoring 39 vr_rdy open collector output . high indicates that the output is regulating 40 vr_hot open collector output indicates the state of the thermal monitoring input. low impedance output indicating a normal status when the voltage of ntc pin is above the specified threshold. this pin will transition to high impedance when the voltage of ntc pin decrease (temperature increase) below the specified threshold. this pin requires an external pullup resistor flag gnd power supply return (qfn flag)
NCP5392 http://onsemi.com 8 pin connections vs. phase count number of phases g4 g3 g2 g1 cs4 ? cs4n cs3 ? cs3n cs2 ? cs2n cs1 ? cs1n 4 phase 4 out phase 3 out phase 2 out phase 1 out phase 4 cs input phase 3 cs input phase 2 cs input phase 1 cs input 3 tie to gnd phase 3 out phase 2 out phase 1 out tie to vccp phase 3 cs input phase 2 cs input phase 1 cs input 2 tie to gnd phase 2 out tie to gnd phase 1 out tie to vccp phase 2 cs input tie to vccp phase 1 cs input maximum ratings electrical informa tion pin symbol v max v min i source i sink comp 5.5 v ? 0.3 v 10 ma 10 ma v drp 5.5 v ? 0.3 v 5 ma 5 ma v+ 5.5 v gnd ? 300 mv 1 ma 1 ma v? gnd + 300 mv gnd ? 300 mv 1 ma 1 ma diffout 5.5 v ? 0.3 v 20 ma 20 ma vr_rdy 5.5 v ? 0.3 v n/a 20 ma vcc 7.0 v ? 0.3 v n/a 10 ma rosc 5.5 v ? 0.3 v 1 ma n/a imon output 1.1 v all other pins 5.5 v ? 0.3 v *all signals referenced to agnd unless otherwise noted. thermal informa tion rating symbol value unit thermal characteristic, qfn package (note 1) r ja 34 c/w operating junction temperature range (note 2) t j 0 to 125 c operating ambient temperature range t a 0 to +85 c maximum storage temperature range t stg ? 55 to +150 c moisture sensitivity level, qfn package msl 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *the maximum package power dissipation must be observed. 1. jesd 51 ? 5 (1s2p direct ? attach method) with 0 lfm. 2. jesd 51 ? 7 (1s2p direct ? attach method) with 0 lfm.
NCP5392 http://onsemi.com 9 electrical characteristics (unless otherwise stated: 0 c < t a < 85 c; 4.75 v < v cc < 5.25 v; all dac codes; c vcc = 0.1 f) parameter test conditions min typ max unit error amplifier input bias current (note 3) ? 200 200 na noninverting voltage range (note 3) 0 1.3 3 v input offset voltage (note 3) v+ = v ? = 1.1 v ? 1.0 ? 1.0 mv open loop dc gain c l = 60 pf to gnd, r l = 10 k to gnd ? 100 db open loop unity gain bandwidth c l = 60 pf to gnd, r l = 10 k to gnd ? 10 ? mhz open loop phase margin c l = 60 pf to gnd, r l = 10 k to gnd ? 80 ? slew rate v in = 100 mv, g = ? 10 v/v, v out = 1.5 v ? 2.5 v, c l = 60 pf to gnd, dc load = 125 a to gnd ? 5 ? v/ s maximum output v oltage i source = 2.0 ma 3.5 ? ? v minimum output v oltage i sink = 0.2 ma ? ? 50 mv output source current (note 3) v out = 3.5 v 2 ? ? ma output sink current (note 3) v out = 1.0 v 2 ? ? ma differential summing amplifier vsn input bias current vsn voltage = 0 v 30 a vsp input resistance drvon = low drvon = high 1.5 17 k vsp input bias voltage drvon = low drvon = high 0.09 0.66 v input voltage range (note 3) ? 0.3 ? 3.0 v ? 3 db bandwidth c l = 80 pf to gnd, r l = 10 k to gnd ? 10 ? mhz closed loop dc gain vs to diffout vs+ to vs ? = 0.5 to 1.6 v 0.98 1.0 1.025 v/v maximum output v oltage i source = 2 ma 3.0 ? ? v minimum output v oltage i sink = 2 ma ? ? 0.5 v output source current (note 3) v out = 3 v 2.0 ? ? ma output sink current (note 3) v out = 0.5 v 2.0 ? ? ma internal offset voltage offset voltage to the (+) pin of the error amp and the vdrp pin ? 1.30 ? v vdroop amplifier input bias current (note 3) ? 200 200 na non ? inverting voltage range (note 3) 0 1.3 3 v input offset voltage (note 3) v+ = v ? = 1.1 v ? 4.0 ? 4.0 mv open loop dc gain c l = 20 pf to gnd including esd, r l = 1 k to gnd ? 100 db open loop unity gain bandwidth c l = 20 pf to gnd including esd, r l = 1 k to gnd ? 10 ? mhz slew rate c l = 20 pf to gnd including esd, r l = 1 k to gnd ? 5 ? v/ s maximum output v oltage i source = 4.0 ma 3 ? ? v minimum output v oltage i sink = 1.0 ma ? ? 1 v output source current (note 3) v out = 3.0 v 4 ? ? ma output sink current (note 3) v out = 1.0 v 1 ? ? ma 3. guaranteed by design, not tested in production.
NCP5392 http://onsemi.com 10 electrical characteristics (unless otherwise stated: 0 c < t a < 85 c; 4.75 v < v cc < 5.25 v; all dac codes; c vcc = 0.1 f) parameter unit max typ min test conditions cssum amplifier current sense input to cssum gain ? 60 mv < cs < 60 mv ? 4.00 ? 3.88 ? 3.76 v/v current sense input to cssum ? 3 db bandwidth c l = 10 pf to gnd, r l = 10 k to gnd ? 4 ? mhz current sense input to cssum output slew rate v in = 25 mv, cl = 10 pf to gnd, load = 1 k to 1.3 v ? 4 ? v/s current summing amp output of fset voltage csx ? csnx = 0, csx = 1.1 v ? 15 ? +15 mv maximum cssum output v oltage csx ? csxn = ? 0.15 v (all phases) i source = 1 ma 3.0 ? ? v minimum cssum output v oltage csx ? csxn = 0.066 v (all phases) i sink = 1 ma ? ? 0.3 v output source current (note 3) v out = 3.0 v 1 ? ? ma output sink current (note 3) v out = 0.3 v 1 ? ? ma psi (power saving control, active low) enable high input leakage current external 1 k pullup to 3.3 v ? ? 1.0 a upper threshold v upper ? 650 770 mv lower threshold v lower 450 550 ? mv hysteresis v upper ? v lower ? 100 ? mv drvon output high v oltage sourcing 500 a 3.0 ? ? v sourcing current for output high v cc = 5 v ? 2.5 4.0 ma output low voltage sinking 500 a ? ? 0.7 v sinking current for output low 2.5 ? ? ma delay time propagation delay from en low to drvon ? 10 ? ns rise time c l (pcb) = 20 pf, v o = 10% to 90% ? 130 ? ns fall time c l (pcb) = 20 pf, v o = 10% to 90% ? 10 ? ns internal pulldown resistance 35 70 140 k v cc voltage when drvon output v alid ? ? 2.0 v current sense amplifiers input bias current (note 3) csx = csxn = 1.4 v ? 0 ? na common mode input voltage range (note 3) ? 0.3 ? 2.0 v differential mode input voltage range (note 3) ? 120 ? 120 mv input offset voltage csx = csxn = 1.1 v, ? 1.0 ? 1.0 mv current sense input to pwm gain (note 3) 0 v < csx ? csxn < 0.1 v, 5.7 6.0 6.3 v/v current sharing offset cs1 to csx all vid codes ? 2.5 ? 2.5 mv imon v drp to imon gain 1.325 v< v drp < 1.8 v 1.98 2 2.02 v/v v drp to imon ? 3 db bandwidth c l = 30 pf to gnd, r l = 100 k to gnd ? 4 mhz output referred of fset voltage v drp = 1.6 v, i source = 0 ma 81 90 99 mv minimum output v oltage v drp = 1.2 v, i sink = 100 a ? ? 0.11 v 3. guaranteed by design, not tested in production.
NCP5392 http://onsemi.com 11 electrical characteristics (unless otherwise stated: 0 c < t a < 85 c; 4.75 v < v cc < 5.25 v; all dac codes; c vcc = 0.1 f) parameter unit max typ min test conditions imon output source current (note 3) v out = 1 v 300 ? ? a output sink current (note 3) v out = 0.3 v 300 ? ? a maximum clamp v oltage v drp voltage = 2 v, r load = 100 k ? ? 1.15 v oscillator switching frequency range (note 3) 100 ? 1000 khz switching frequency accuracy 2 ? or 4 ? phase r osc = 49.9 k 200 ? 224 khz r osc = 24.9 k 374 ? 414 r osc = 10 k 800 ? 978 switching frequency accuracy 3 ? phase r osc = 49.9 k 191 ? 234 khz r osc = 24.9 k 354 ? 434 r osc = 10 k 755 ? 1000 r osc output voltage 1.95 2.01 2.065 v modulators (pwm comparators) minimum pulse width f sw = 800 khz ? 30 ? ns propagation delay 20 mv of overdrive ? 10 ? ns 0% duty cycle comp voltage when the pwm outputs remain lo ? 1.3 ? v 100% duty cycle comp voltage when the pwm outputs remain hi ? 2.3 ? v pwm ramp duty cycle matching between any two phases ? 90 ? % pwm phase angle error (note 3) between adjacent phases 15 ? 15 vr_rdy (power good) output vr_rdy output saturation voltage i pgd = 10 ma, ? ? 0.4 v vr_rdy rise time (note 3) external pullup of 1 k to 1.25 v, c tot = 45 pf, v o = 10% to 90% ? 100 150 ns vr_rdy output voltage at powerup (note 3) vr_rdy pulled up to 5 v via 2k , t r(vcc) 3 x t r(5v) 100 s t r(v cc ) 20 ms ? ? 1.0 v vr_rdy high ? output leakage current (note 3) vr_rdy = 5.5 v via 1 k ? ? 0.2 a vr_rdy upper threshold voltage vcore increasing, dac = 1.3 v ? 310 270 mv below dac vr_rdy lower threshold voltage vcore decreasing dac = 1.3 v 410 370 mv below dac vr_rdy rising delay vcore increasing ? 500 ? s vr_rdy falling delay vcore decreasing ? 5 ? s pwm outputs output high v oltage sourcing 500 a 3.0 ? ? v mid output v oltage 1.4 1.5 1.6 v output low voltage sinking 500 a ? ? 0.7 v delay + fall time (note 3) c l (pcb) = 50 pf , vo = v cc to gnd ? 10 15 ns delay + rise time (note 3) c l (pcb) = 50 pf , vo = gnd to v cc ? 10 15 ns 3. guaranteed by design, not tested in production.
NCP5392 http://onsemi.com 12 electrical characteristics (unless otherwise stated: 0 c < t a < 85 c; 4.75 v < v cc < 5.25 v; all dac codes; c vcc = 0.1 f) parameter unit max typ min test conditions pwm outputs output impedance ? hi or lo state resistance to v cc (hi) or gnd (lo) ? 75 ? 2/3/4 ? phase detection gate pin source current 60 80 150 a gate pin threshold voltage 210 240 265 mv phase detect timer 15 20 27 s digital soft ? start soft ? start ramp time dac = 0 to dac = 1.1 v 1.0 ? 1.5 ms vr11 vboot time 400 500 600 s vid7/vr1 1/amd input vid upper threshold v upper ? 650 800 mv vid lower threshold v lower 300 550 ? mv vid hysteresis v upper ? v lower ? 100 ? mv amd input bias current 10 ? 20 a vr11 input bias current (note 3) 200 na delay before latching vid change (vid de ? skewing) (note 3) measured from the edge of the 1 st vid change 200 ? 300 ns amd upper threshold (note 3) 2.9 v amd lower threshold (note 3) 2.4 v enable input enable high input leakage current (note 3) pullup to 1.3 v ? ? 200 na vr11 rising threshold ? 650 770 mv vr11 falling threshold 450 550 ? mv vr11 total hysteresis rising ? falling threshold ? 100 ? mv amd upper threshold ? 1.3 1.5 v amd lower threshold 0.9 1.1 ? v amd total hysteresis rising ? falling threshold 200 mv enable delay time measure time from enable transitioning hi to when output begins 2.5 4.0 ms current limit i lim to v drp gain between v drp ? v dfb = 450 mv and v drp ? v dfb = 650 mv 0.95 1 1.05 v/v i lim to v drp gain in psi 4 phase between v drp ? v dfb = 450 mv and v drp ? v dfb = 650 mv ? 0.25 ? v/v i lim to v drp gain in psi 3 phase between v drp ? v dfb = 450 mv and v drp ? v dfb = 650 mv ? 0.33 ? v/v i lim to v drp gain in psi 2 phase between v drp ? v dfb = 450 mv and v drp ? v dfb = 650 mv ? 0.5 ? v/v i lim offset v drp ? v dfb = 520 mv ? 50 0 50 mv delay ? 100 ? ns overvoltage protection vr11 overvoltage threshold dac +150 dac +185 dac +200 mv vr11 psi overvoltage threshold (note 3) (1.6 v dac) +150 (1.6 v dac) +200 mv amd overvoltage threshold (note 3) dac +200 dac +235 dac +305 mv 3. guaranteed by design, not tested in production.
NCP5392 http://onsemi.com 13 electrical characteristics (unless otherwise stated: 0 c < t a < 85 c; 4.75 v < v cc < 5.25 v; all dac codes; c vcc = 0.1 f) parameter unit max typ min test conditions overvoltage protection amd psi overvoltage threshold (note 3) (1.55 v dac) +200 (1.55 v dac) +235 (1.55 v dac) +305 mv delay 100 ns undervoltage protection vcc uvlo start threshold 4 4.25 4.5 v vcc uvlo stop threshold 3.8 4.05 4.3 v vcc uvlo hysteresis 200 mv vr_hot vr_hot upper voltage threshold 19.6 k p.u. to v cc , 68 k ntc , = 3740 0.257 0.268 0.280 v cc vr_hot lower voltage threshold 19.6 k p.u. to vcc, 68 k ntc , = 3740 0.316 0.329 0.343 v cc vr_hot output voltages at power ? up (note 3) external pull ? up resistor of 2 k to 5 v, t r_vcc 3 x t r_5 v , 100 s t r_vcc 20 ms ? ? 1.0 v vr_hot saturation output voltage i sink = 4 ma ? ? 0.3 v vr_hot output leakage current ? ? 1 a ntc pin bias current ? ? 1 a 12vmon uvlo 12vmon (high threshold) v cc valid ? 0.77 0.82 v 12vmon (low threshold) v cc valid 0.66 0.68 ? v dac (feed forward function) output source current v out = 3 v 0.25 ma output sink current v out = 0.3 v 1.5 ma max output voltage (note 3) i source = 2 ma 3 v min output voltage (note 3) i sink = 2 ma 0.5 v vrm 11 dac positive dac slew rate 11 ? 16.5 mv/ s system voltage accuracy (dac value has a 19 mv offset over the output v alue) 1.0 v < dac < 1.6 v 0.8 v < dac < 1.0 v 0.5 v < dac < 0.8 v ? ? ? ? ? ? 0.5 5 8 % mv mv amd dac positive dac slew rate ? 3.5 5 mv/ s system voltage accuracy (dac value has a 19 mv offset over the output v alue) 1.0 v < dac < 1.55 v 0.3750 < dac < 0.8 v ? ? 0.5 5.0 % mv v cc v cc operating current en low, no pwm ? 15 30 ma 3. guaranteed by design, not tested in production.
NCP5392 http://onsemi.com 14 table 1. vrm11 vid codes vid7 800 mv vid6 400 mv vid5 200 mv vid4 100 mv vid3 50 mv vid2 25 mv vid1 12.5 mv vid0 6.25 mv voltage (v) hex 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 01 0 0 0 0 0 0 1 0 1.60000 02 0 0 0 0 0 0 1 1 1.59375 03 0 0 0 0 0 1 0 0 1.58750 04 0 0 0 0 0 1 0 1 1.58125 05 0 0 0 0 0 1 1 0 1.57500 06 0 0 0 0 0 1 1 1 1.56875 07 0 0 0 0 1 0 0 0 1.56250 08 0 0 0 0 1 0 0 1 1.55625 09 0 0 0 0 1 0 1 0 1.55000 0a 0 0 0 0 1 0 1 1 1.54375 0b 0 0 0 0 1 1 0 0 1.53750 0c 0 0 0 0 1 1 0 1 1.53125 0d 0 0 0 0 1 1 1 0 1.52500 0e 0 0 0 0 1 1 1 1 1.51875 0f 0 0 0 1 0 0 0 0 1.51250 10 0 0 0 1 0 0 0 1 1.50625 11 0 0 0 1 0 0 1 0 1.50000 12 0 0 0 1 0 0 1 1 1.49375 13 0 0 0 1 0 1 0 0 1.48750 14 0 0 0 1 0 1 0 1 1.48125 15 0 0 0 1 0 1 1 0 1.47500 16 0 0 0 1 0 1 1 1 1.46875 17 0 0 0 1 1 0 0 0 1.46250 18 0 0 0 1 1 0 0 1 1.45625 19 0 0 0 1 1 0 1 0 1.45000 1a 0 0 0 1 1 0 1 1 1.44375 1b 0 0 0 1 1 1 0 0 1.43750 1c 0 0 0 1 1 1 0 1 1.43125 1d 0 0 0 1 1 1 1 0 1.42500 1e 0 0 0 1 1 1 1 1 1.41875 1f 0 0 1 0 0 0 0 0 1.41250 20 0 0 1 0 0 0 0 1 1.40625 21 0 0 1 0 0 0 1 0 1.40000 22 0 0 1 0 0 0 1 1 1.39375 23 0 0 1 0 0 1 0 0 1.38750 24 0 0 1 0 0 1 0 1 1.38125 25 0 0 1 0 0 1 1 0 1.37500 26 0 0 1 0 0 1 1 1 1.36875 27 0 0 1 0 1 0 0 0 1.36250 28 0 0 1 0 1 0 0 1 1.35625 29 0 0 1 0 1 0 1 0 1.35000 2a 0 0 1 0 1 0 1 1 1.34375 2b 0 0 1 0 1 1 0 0 1.33750 2c 0 0 1 0 1 1 0 1 1.33125 2d 0 0 1 0 1 1 1 0 1.32500 2e 0 0 1 0 1 1 1 1 1.31875 2f
NCP5392 http://onsemi.com 15 table 1. vrm11 vid codes vid7 800 mv hex voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 0 0 1 1 0 0 0 0 1.31250 30 0 0 1 1 0 0 0 1 1.30625 31 0 0 1 1 0 0 1 0 1.30000 32 0 0 1 1 0 0 1 1 1.29375 33 0 0 1 1 0 1 0 0 1.28750 34 0 0 1 1 0 1 0 1 1.28125 35 0 0 1 1 0 1 1 0 1.27500 36 0 0 1 1 0 1 1 1 1.26875 37 0 0 1 1 1 0 0 0 1.26250 38 0 0 1 1 1 0 0 1 1.25625 39 0 0 1 1 1 0 1 0 1.25000 3a 0 0 1 1 1 0 1 1 1.24375 3b 0 0 1 1 1 1 0 0 1.23750 3c 0 0 1 1 1 1 0 1 1.23125 3d 0 0 1 1 1 1 1 0 1.22500 3e 0 0 1 1 1 1 1 1 1.21875 3f 0 1 0 0 0 0 0 0 1.21250 40 0 1 0 0 0 0 0 1 1.20625 41 0 1 0 0 0 0 1 0 1.20000 42 0 1 0 0 0 0 1 1 1.19375 43 0 1 0 0 0 1 0 0 1.18750 44 0 1 0 0 0 1 0 1 1.18125 45 0 1 0 0 0 1 1 0 1.17500 46 0 1 0 0 0 1 1 1 1.16875 47 0 1 0 0 1 0 0 0 1.16250 48 0 1 0 0 1 0 0 1 1.15625 49 0 1 0 0 1 0 1 0 1.15000 4a 0 1 0 0 1 0 1 1 1.14375 4b 0 1 0 0 1 1 0 0 1.13750 4c 0 1 0 0 1 1 0 1 1.13125 4d 0 1 0 0 1 1 1 0 1.12500 4e 0 1 0 0 1 1 1 1 1.11875 4f 0 1 0 1 0 0 0 0 1.11250 50 0 1 0 1 0 0 0 1 1.10625 51 0 1 0 1 0 0 1 0 1.10000 52 0 1 0 1 0 0 1 1 1.09375 53 0 1 0 1 0 1 0 0 1.08750 54 0 1 0 1 0 1 0 1 1.08125 55 0 1 0 1 0 1 1 0 1.07500 56 0 1 0 1 0 1 1 1 1.06875 57 0 1 0 1 1 0 0 0 1.06250 58 0 1 0 1 1 0 0 1 1.05625 59 0 1 0 1 1 0 1 0 1.05000 5a 0 1 0 1 1 0 1 1 1.04375 5b 0 1 0 1 1 1 0 0 1.03750 5c 0 1 0 1 1 1 0 1 1.03125 5d 0 1 0 1 1 1 1 0 1.02500 5e 0 1 0 1 1 1 1 1 1.01875 5f
NCP5392 http://onsemi.com 16 table 1. vrm11 vid codes vid7 800 mv hex voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 0 1 1 0 0 0 0 0 1.01250 60 0 1 1 0 0 0 0 1 1.00625 61 0 1 1 0 0 0 1 0 1.00000 62 0 1 1 0 0 0 1 1 0.99375 63 0 1 1 0 0 1 0 0 0.98750 64 0 1 1 0 0 1 0 1 0.98125 65 0 1 1 0 0 1 1 0 0.97500 66 0 1 1 0 0 1 1 1 0.96875 67 0 1 1 0 1 0 0 0 0.96250 68 0 1 1 0 1 0 0 1 0.95625 69 0 1 1 0 1 0 1 0 0.95000 6a 0 1 1 0 1 0 1 1 0.94375 6b 0 1 1 0 1 1 0 0 0.93750 6c 0 1 1 0 1 1 0 1 0.93125 6d 0 1 1 0 1 1 1 0 0.92500 6e 0 1 1 0 1 1 1 1 0.91875 6f 0 1 1 1 0 0 0 0 0.91250 70 0 1 1 1 0 0 0 1 0.90625 71 0 1 1 1 0 0 1 0 0.90000 72 0 1 1 1 0 0 1 1 0.89375 73 0 1 1 1 0 1 0 0 0.88750 74 0 1 1 1 0 1 0 1 0.88125 75 0 1 1 1 0 1 1 0 0.87500 76 0 1 1 1 0 1 1 1 0.86875 77 0 1 1 1 1 0 0 0 0.86250 78 0 1 1 1 1 0 0 1 0.85625 79 0 1 1 1 1 0 1 0 0.85000 7a 0 1 1 1 1 0 1 1 0.84375 7b 0 1 1 1 1 1 0 0 0.83750 7c 0 1 1 1 1 1 0 1 0.83125 7d 0 1 1 1 1 1 1 0 0.82500 7e 0 1 1 1 1 1 1 1 0.81875 7f 1 0 0 0 0 0 0 0 0.81250 80 1 0 0 0 0 0 0 1 0.80625 81 1 0 0 0 0 0 1 0 0.80000 82 1 0 0 0 0 0 1 1 0.79375 83 1 0 0 0 0 1 0 0 0.78750 84 1 0 0 0 0 1 0 1 0.78125 85 1 0 0 0 0 1 1 0 0.77500 86 1 0 0 0 0 1 1 1 0.76875 87 1 0 0 0 1 0 0 0 0.76250 88 1 0 0 0 1 0 0 1 0.75625 89 1 0 0 0 1 0 1 0 0.75000 8a 1 0 0 0 1 0 1 1 0.74375 8b 1 0 0 0 1 1 0 0 0.73750 8c 1 0 0 0 1 1 0 1 0.73125 8d 1 0 0 0 1 1 1 0 0.72500 8e 1 0 0 0 1 1 1 1 0.71875 8f
NCP5392 http://onsemi.com 17 table 1. vrm11 vid codes vid7 800 mv hex voltage (v) vid0 6.25 mv vid1 12.5 mv vid2 25 mv vid3 50 mv vid4 100 mv vid5 200 mv vid6 400 mv 1 0 0 1 0 0 0 0 0.71250 90 1 0 0 1 0 0 0 1 0.70625 91 1 0 0 1 0 0 1 0 0.70000 92 1 0 0 1 0 0 1 1 0.69375 93 1 0 0 1 0 1 0 0 0.68750 94 1 0 0 1 0 1 0 1 0.68125 95 1 0 0 1 0 1 1 0 0.67500 96 1 0 0 1 0 1 1 1 0.66875 97 1 0 0 1 1 0 0 0 0.66250 98 1 0 0 1 1 0 0 1 0.65625 99 1 0 0 1 1 0 1 0 0.65000 9a 1 0 0 1 1 0 1 1 0.64375 9b 1 0 0 1 1 1 0 0 0.63750 9c 1 0 0 1 1 1 0 1 0.63125 9d 1 0 0 1 1 1 1 0 0.62500 9e 1 0 0 1 1 1 1 1 0.61875 9f 1 0 1 0 0 0 0 0 0.61250 a0 1 0 1 0 0 0 0 1 0.60625 a1 1 0 1 0 0 0 1 0 0.60000 a2 1 0 1 0 0 0 1 1 0.59375 a3 1 0 1 0 0 1 0 0 0.58750 a4 1 0 1 0 0 1 0 1 0.58125 a5 1 0 1 0 0 1 1 0 0.57500 a6 1 0 1 0 0 1 1 1 0.56875 a7 1 0 1 0 1 0 0 0 0.56250 a8 1 0 1 0 1 0 0 1 0.55625 a9 1 0 1 0 1 0 1 0 0.55000 aa 1 0 1 0 1 0 1 1 0.54375 ab 1 0 1 0 1 1 0 0 0.53750 ac 1 0 1 0 1 1 0 1 0.53125 ad 1 0 1 0 1 1 1 0 0.52500 ae 1 0 1 0 1 1 1 1 0.51875 af 1 0 1 1 0 0 0 0 0.51250 b0 1 0 1 1 0 0 0 1 0.50625 b1 1 0 1 1 0 0 1 0 0.50000 b2 1 1 1 1 1 1 1 0 off fe 1 1 1 1 1 1 1 1 off ff
NCP5392 http://onsemi.com 18 table 2. amd processor 6 ? bit vid code (vid) codes nominal v out units v id5 v id4 v id3 v id2 v id1 v id0 0 0 0 0 0 0 1.550 v 0 0 0 0 0 1 1.525 v 0 0 0 0 1 0 1.500 v 0 0 0 0 1 1 1.475 v 0 0 0 1 0 0 1.450 v 0 0 0 1 0 1 1.425 v 0 0 0 1 1 0 1.400 v 0 0 0 1 1 1 1.375 v 0 0 1 0 0 0 1.350 v 0 0 1 0 0 1 1.325 v 0 0 1 0 1 0 1.300 v 0 0 1 0 1 1 1.275 v 0 0 1 1 0 0 1.250 v 0 0 1 1 0 1 1.225 v 0 0 1 1 1 0 1.200 v 0 0 1 1 1 1 1.175 v 0 1 0 0 0 0 1.150 v 0 1 0 0 0 1 1.125 v 0 1 0 0 1 0 1.100 v 0 1 0 0 1 1 1.075 v 0 1 0 1 0 0 1.050 v 0 1 0 1 0 1 1.025 v 0 1 0 1 1 0 1.000 v 0 1 0 1 1 1 0.975 v 0 1 1 0 0 0 0.950 v 0 1 1 0 0 1 0.925 v 0 1 1 0 1 0 0.900 v 0 1 1 0 1 1 0.875 v 0 1 1 1 0 0 0.850 v 0 1 1 1 0 1 0.825 v 0 1 1 1 1 0 0.800 v 0 1 1 1 1 1 0.775 v 1 0 0 0 0 0 0.7625 v 1 0 0 0 0 1 0.7500 v 1 0 0 0 1 0 0.7375 v 1 0 0 0 1 1 0.7250 v 1 0 0 1 0 0 0.7125 v 1 0 0 1 0 1 0.7000 v 1 0 0 1 1 0 0.6875 v 1 0 0 1 1 1 0.6750 v 1 0 1 0 0 0 0.6625 v
NCP5392 http://onsemi.com 19 table 2. amd processor 6 ? bit vid code (vid) codes units nominal v out v id5 v id0 v id1 v id2 v id3 v id4 1 0 1 0 0 1 0.6500 v 1 0 1 0 1 0 0.6375 v 1 0 1 0 1 1 0.6250 v 1 0 1 1 0 0 0.6125 v 1 0 1 1 0 1 0.6000 v 1 0 1 1 1 0 0.5875 v 1 0 1 1 1 1 0.5750 v 1 1 0 0 0 0 0.5625 v 1 1 0 0 0 1 0.5500 v 1 1 0 0 1 0 0.5375 v 1 1 0 0 1 1 0.5250 v 1 1 0 1 0 0 0.5125 v 1 1 0 1 0 1 0.5000 v 1 1 0 1 1 0 0.4875 v 1 1 0 1 1 1 0.4750 v 1 1 1 0 0 0 0.4625 v 1 1 1 0 0 1 0.4500 v 1 1 1 0 1 0 0.4375 v 1 1 1 0 1 1 0.4250 v 1 1 1 1 0 0 0.4125 v 1 1 1 1 0 1 0.4000 v 1 1 1 1 1 0 0.3875 v 1 1 1 1 1 1 0.3750 v
NCP5392 http://onsemi.com 20 functional description general the NCP5392 provides up to four ? phase buck solution which combines differential voltage sensing, differential phase current sensing, and adaptive voltage positioning to provide accurately regulated power necessary for both intel vr11.1 and amd cpu power system. NCP5392 has been designed to work with the ncp5359 driver. remote output sensing amplifier(rsa) a true differential amplifier allows the NCP5392 to measure v core voltage feedback with respect to the v core ground reference point by connecting the v core reference point to vsp, and the v core ground reference point to vsn. this configuration keeps ground potential differences between the local controller ground and the v core ground reference point from affecting regulation of v core between v core and v core ground reference points. the rsa also subtracts the dac (minus vid offset) voltage, thereby producing an unamplified output error voltage at the diffout pin. this output also has a 1.3 v bias voltage as the floating ground to allow both positive and negative error voltages. precision programmable dac a precision programmable dac is provided and system trimmed. this dac has 0.5% accuracy over the entire operating temperature range of the part. the dac can be programmed to support either intel vr11 or amd 6 ? bit vid code specifications. high performance v oltage error amplifier the error amplifier is designed to provide high slew rate and bandwidth. although not required when operating as the controller of a voltage regulator, a capacitor from comp to vfb is required for stable unity gain test configurations. gate driver outputs and 2/3/4 phase operation the part can be configured to run in 2 ? , 3 ? , or 4 ? phase mode. in 2 ? phase mode, phases 1 and 3 should be used to drive the external gate drivers as shown in the 2 ? phase applications schematic, g2 and g4 must be grounded. in 3 ? phase mode, gate output g4 must be grounded as shown in the 3 ? phase applications schematic. in 4 ? phase mode all 4 gate outputs are used as shown in the 4 ? phase applications schematic. the current sense inputs of unused channels should be connected to vccp shown in the application schematics. please refer to table ?pin connections vs. phase counts? for details. differential current sense amplifiers and summing amplifier four differential amplifiers are provided to sense the output current of each phase. the inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (g1, g2, g3, or g4). if a phase is unused, the differential inputs to that phase?s current sense amplifier must be shorted together and connected to the output as shown in the 2 ? and 3 ? phase application schematics. the current signals sensed from inductor dcr are fed into a summing amplifier to have a summed ? up output (cssum). signal of cssum combines information of total current of all phases in operation. the outputs of current sense amplifiers control three functions. first, the summing current signal (ccsum) of all phases will go through droop amplifier and join the voltage feedback loop for output voltage positioning. second, the output signal from droop amplifier also goes to ilim amplifier to monitor the output current limit. finally, the individual phase current contributes to the current balance of all phases by offsetting their ramp signals of pwm comparators. thermal compensation amplifier with vdrp and vdfb pins thermal compensation amplifier is an internal amplifier in the path of droop current feedback for additional adjustment of the gain of summing current and temperature compensation. the way thermal compensation is implemented separately ensures minimum interference to the voltage loop compensation network. oscillator and t riangle wave generator a programmable precision oscillator is provided. the oscillator ?s frequency is programmed by the resistance connected from the rosc pin to ground. the user will usually form this resistance from two resistors in order to create a voltage divider that uses the rosc output voltage as the reference for creating the current limit setpoint voltage. the oscillator frequency range is 100 khz per phase to 1.0 mhz per phase. the oscillator generates up to 4 symmetrical triangle waveforms with amplitude between 1.3 v and 2.3 v. the triangle waves have a phase delay between them such that for 2 ? , 3 ? and 4 ? phase operation the pwm outputs are separated by 180, 120, and 90 angular degrees, respectively.
NCP5392 http://onsemi.com 21 pwm comparators with hysteresis four pwm comparators receive an error signal at their noninverting input. each comparator receives one of the triangle waves at its inverting output. the output of each comparator generates the pwm outputs g1, g2, g3, and g4. during steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by v out /v in . during a transient event, both high and low comparator output transitions shift phase to the points where the error signal intersects the down and up ramp of the triangle wave. protection features undervoltage lockout (vcc and 12vmon) an undervoltage lockout (uvlo) senses the v cc input directly. 12 v uvlo senses the 12 v power supply by connecting it to the 12vmon pin through an appropriate resistor divider . during power ? up, both the vcc input and 12vmon are monitored, and the pwm outputs and the soft ? start circuit are disabled until both input voltages exceed the threshold voltages of their individual uvlo comparators. the uvlo comparators both incorporate hysteresis to avoid chattering. overcurrent shutdown a programmable overcurrent function is incorporated within the ic. a comparator and latch make up this function. the inverting input of the comparator is connected to the ilim pin. the voltage at this pin sets the maximum output current the converter can produce. the rosc pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. although not actually disabled, tying the ilim pin directly to the rosc pin sets the limit above useful levels ? effectively disabling overcurrent shutdown. the comparator noninverting input is the summed current information from the vdrp minus offset voltage. the overcurrent latch is set when the current information exceeds the voltage at the ilim pin. the outputs are pulled low, and the soft ? start is pulled low. the outputs will remain disabled until the v cc voltage is removed and re ? applied, or the enable input is brought low and then high. output overvoltage and undervoltage protection and power good monitor an output voltage monitor is incorporated. during normal operation, if the output voltage is 180 mv (typical) over the dac voltage, the vr_rdy goes low, the drvon signal remains high, the pwm outputs are set low. the outputs will remain disabled until the v cc voltage is removed and reapplied. during normal operation, if the output voltage falls more than 350 mv below the dac setting, the vr_rdy pin will be set low until the output voltage rises. soft ? start there are two possible soft ? start modes: amd and vr11. amd mode simply ramps v core from 0 v directly to the dac setting at a fixed rate. the vr11 mode ramps v core to 1.1 v boot voltage at a fixed rate of 0.8 mv/ s, pauses at 1.1 v for around 500 s, reads the vid pins to determine the dac setting. then ramps v core to the final dac setting at the dynamic vid slew rate of up to 12.5 mv/ s. typical amd and vr11 soft ? start sequences are shown in the following graphs (figure 9 and 10). application information the NCP5392 demo board for the NCP5392 is available by request. it is configured as a four phase solution with decoupling designed to provide a 1 m load line under a 100 a step load. startup procedure start by installing the test tool software. it is best to power the test tool from a separate atx power supply. the test tool should be set to a valid vid code of 0.5 v or above in order for the controller to start. consult the vtt help manual for more detailed instruction. step load testing the vtt tool is used to generate the d i /d t step load. select the dynamic loading option in the vtt test tool software. set the desired step load size, frequency, duty, and slew rate. see figure 6. figure 6. typical load step response (full load, 35 a ? 100 a) dynamic vid testing the vtt tool provides for vid stepping based on the intel requirements. select the dynamic vid option. before enabling the test set the lowest vid to 0.5 v or greater and set the highest vid to a value that is greater than the lowest vid selection, then enable the test. see figures 7 and 8.
NCP5392 http://onsemi.com 22 figure 7. 1.6 v to 0.5 v dynamic vid response figure 8. dynamic vid settling time rising (ch1: vid1, ch2: dac, ch3:vccp) design methodology decoupling the v cc pin on the ic an rc input filter is required as shown in the v cc pin to minimize supply noise on the ic. the resistor should be sized such that it does not generate a large voltage drop between 5 v supply and the ic. understanding soft ? start the controller supports two different startup routines. an amd ramp to the initial vid code, or a vr11 ramp to the 1.1 v boot voltage, with a pause to capture the vid code then resume ramping to target value based on internal slew rate limit. the initial ramp rate was set to be 0.8 mv/ s. figure 9. vr11.1 startup figure 10. amd startup programming the current limit and the oscillator frequency the demo board is set for an operating frequency of approximately 330 khz. the r osc pin provides a 2.0 v reference voltage which is divided down with a resistor divider and fed into the current limit pin ilim. then calculate the individual rlim1 and rlim2 values for the divider. the series resistors rlim1 and rlim2 sink current from the ilim pin to ground. this current is internally mirrored into a capacitor to create an oscillator. the period is proportional to the resistance and frequency is inversely proportional to the total resistance. the total resistance may be estimated by equation 1. this equation is valid for the individual phase frequency in both three and four phase mode. r osc 20947 f sw 1.1262 (eq. 1) 30.5 k 20947 330 1.1262
NCP5392 http://onsemi.com 23 0 10 20 30 40 50 60 100 1000 freq ? khz rosc ? kohm calculation real figure 11. rosc vs. frequency the current limit function is based on the total sensed current of all phases multiplied by a controlled gain (acssum*adrp). dcr sensed inductor current is a function of the winding temperature. the best approach is to set the maximum current limit based on expected average maximum temperature of the inductor windings, dcr tmax dcr 25c (1 0.00393 (t max 25)) (eq. 2) for multiphase controller, the ripple current can be calculated as, ipp (v in n v out ) v out l f sw v in (eq. 3) therefore calculate the current limit voltage as below, v limit a cssum a drp dcr tmax (i min_ocp 0.5 ipp) (eq. 4) v limit a cssum a drp dcr tmax i min_ocp 0.5 (v in n v out ) v out l f sw v in in equation 4, a cssum and a drp are the gain of current summing amplifier and droop amplifier. figure 12. acssum and adrp + i1 i2 i3 i4 ilim acssum adrp ocp event + ? + ? riso1 riso2 rt2 rsum rnor as introduced before, v limit comes from a resistor divider connected to rosc pin, thus, v limit 2v r lim2 r lim1 r lim2 coepsi (eq. 5) a cssum 4 a drp r nor (r iso1 r iso2 r t2 ) (r nor r iso1 r iso2 r t2 ) r sum (eq. 6) r iso1 and r iso2 are in series with r t2 , the ntc temperature sense resistor placed near inductor. r sum is the resistor connecting between pin vdfb and pin cssum. if psi = 1, psi function is off, the current limit follows the equation 7; if psi = 0, the power saving mode will be enabled, coepsi is a coefficient for the current limiting related with power saving function (psi), the current limit can be calculated from equation 8. coepsi value is one over the original phase count n. refer to the psi and phase shedding section for more details.
NCP5392 http://onsemi.com 24 final equations for the current limit threshold final equations are described based on two conditions: normal mode and psi mode. i limit (normal) 2v r lim2 r lim1 r lim2 4 r nor (r iso1 r iso2 r t2 ) (r nor r iso1 r iso2 r t2 ) r sum dcr 25c (1 0.00393 (t inductor 25)) 0.5 (v in n v out ) v out l f sw v in (eq. 7) i limit (psi) 2v r lim2 r lim1 r lim2 coepsi 4 r nor (r iso1 r iso2 r t2 ) (r nor r iso1 r iso2 r t2 ) r sum dcr 25c (1 0.00393 (t inductor 25)) 0.5 (v in v out ) v out l f sw v in (eq. 8) n is the number of phases involved in the circuit. the inductors on the demo board have a dcr at 25 c of 0.6 m . selecting the closest available values of 21.3 k for r lim1 and 9.28 k for r lim2 yields a nominal operating frequency of 330 khz. select r iso 1 = 1 k, r iso2 = 1 k, r t2 = 10 k (25 c), r nor /r sum = 2, (refer to application diagram). that results to an approximate current limit of 133 a at 100 c for a four phase operation and 131 a at 25 c. the total sensed current can be observed as a scaled voltage at the vdrp with a positive no ? load offset of approximately 1.3 v. inductor selection when using inductor current sensing it is recommended that the inductor does not saturate by more than 10% at maximum load. the inductor also must not go into hard saturation before current limit trips. the demo board includes a four phase output filter using the t44 ? 8 core from micrometals with 3 turns and a dcr target of 0.6 m @ 25 c. smaller dcr values can be used, however, current sharing accuracy and droop accuracy decrease as dcr decreases. use the NCP5392 design aide for regulation accuracy calculations for specific value of dcr. inductor current sensing compensation the NCP5392 uses the inductor current sensing method. an rc filter is selected to cancel out the impedance from inductor and recover the current information through the inductor?s dcr. this is done by matching the rc time constant of the sensing filter to the l/dcr time constant. the first cut approach is to use a 0.1 f capacitor for c and then solve for r. r sense (t) l 0.1 f dcr 25c (1 0.00393(t 25)) (eq. 9) because the inductor value is a function of load and inductor temperature final selection of r is best done experimentally on the bench by monitoring the v droop pin and performing a step load test on the actual solution.
NCP5392 http://onsemi.com 25 simple average spice model a simple state average model shown in figure 13 can be used to determine a stable solution and provide insight into the control system. figure 13. NCP5392 average spice model rsum 1k ? + + ? e1 e gain = {6} l {185e ? 9/4} 1 2 rdfb 2k lbrd 100p 1 2 dcr {0.6e ? 3/4} rbrd 0.75m esrbulk {7e ? 3/6} voff eslbulk {3.5e ? 9/6} 1 2 cbulk {560e ? 6*6} esrcer {1.5e ? 3/18} eslcer {1.5e ? 9/18} 1 2 ccer {22e ? 6*18} i1 td = 100u tf = 50n pw = 100u per = 200u i1 = 50 i2 = 110 tr = 50n 0adc 0aac 0 r9 1k c6 10.6p 12 0 vramp_min 1.3v voffset 1.3v r10 2k rfb 1k rfb1 69.8 rf 2.2k cfb1 680p ch 22p cf 1.8n r12 5.11k { ? 2/3*4} 1e3 r6 1k c4 10.6p r11 1k v3 12v 0 voff 0 0 0 0 0 1e3 0 gain = 1 r8 1k c5 10.6p vdrp voff cdac 12n vdac ac = 0 tran = pulse dc = 1.2v rdac 50 vdrp vout unity gain bw=15mhz voff cdfb 22p 1e3 imon (0 0.05 400u 5u 5u 500u 1000u) compensation and output filter design if the required output filter and switching frequency are significantly different, it?s best to use the available pspice models to design the compensation and output filter from scratch. the design target for this demo board was 1.0 m up to 2.0 mhz. the phase switching frequency is currently set to 330 khz. it can easily be seen that the board impedance of 0.75 m between the load and the bulk capacitance has a large effect on the output filter. in this case the six 560 f bulk capacitors have an esr of 7.0 m . thus the bulk esr plus the board impedance is 1.15 m + 0.75 m or 1.9 m . the actual output filter impedance does not drop to 1.0 m until the ceramic breaks in at over 375 khz. the controller must provide some loop gain slightly less than one out to a frequency in excess 300 khz. at frequencies below where the bulk capacitance esr breaks with the bulk capacitance, the dc ? dc converter must have sufficiently high gain to control the output impedance completely. standard type ? 3 compensation works well with the NCP5392.
NCP5392 http://onsemi.com 26 figure 14. NCP5392 circuit frequency response ? 100 ? 80 ? 60 ? 40 ? 20 0 20 40 60 80 100 1000 10000 100000 1000000 10000000 frequency db zout open loop zout closed loop open loop gain with current loop closed voltage loop compensation gain 1mohm the goal is to compensate the system such that the resulting gain generates constant output impedance from dc up to the frequency where the ceramic takes over holding the impedance below 1.0 m . see the example of the locations of the poles and zeros that were set to optimize the model above. by matching the following equations a good set of starting compensation values can be found for a typical mixed bulk and ceramic capacitor type output filter. 1 2 cf rf 1 2 (rbrd esr bulk ) c bulk (eq. 10) 1 2 cfb1 (rfb1 rfb) 1 2 c cer (rbrd esr bulk ) (eq. 11) r fb should be set to provide optimal thermal compensation in conjunction with thermistor r t2 , r iso1 and r iso2 . with r fb set to 1.0 k , r fb1 is usually set to 100 for maximum phase boost, and the value of rf is typically set to 3.0 k . droop injection and thermal compensation the vdrp signal is generated by summing the sensed output currents for each phase. a droop amplifier is added to adjust the total gain to approximately eight. vdrp is externally summed into the feedback network by the resistor rdrp. this introduces an offset which is proportional to the output current thereby forcing a controlled, resistive output impedance. + ? 1.3 v cfb1 ch rfb1 rfb rf error amp + + csx + ? gain = 1 droop amp + ? pwm comparator cf riso2 riso1 rsx rdrp rl i bias + ? 1.3 v rsum rnor + ? cssum amp figure 15. droop injection and thermal compensation gain = 4 1.3 v rt rdrp determines the target output impedance by the basic equation: v out i out z out r fb dcr a cssum a drp r drp (eq. 12) r drp r fb dcr a cssum a drp z out (eq. 13) the value of the inductor?s dcr is a function of temperature according to the equation 14: dcr (t) dcr 25c (1 0.00393 (t 25)) (eq. 14)
NCP5392 http://onsemi.com 27 actual dcr increases by temperature, the system can be thermally compensated to cancel this effect to a great degree by adding an ntc in parallel with r nor to reduce the droop gain as the temperature increases. the ntc device is nonlinear. putting a resistor in series with the ntc helps make the device appear more linear with temperature. the series resistor is split and inserted on both sides of the ntc to reduce noise injection into the feedback loop. the recommended total value for r iso1 plus r iso2 is approximately 1.0 k . the output impedance varies with inductor temperature by the equation: z out (t) r fb dcr 25c (1 0.00393 (t 25)) a cssum a drp r drp (eq. 15) by including the ntc r t2 and the series isolation resistors the new equation becomes: z out (t) r fb dcr 25c (1 0.00393 (t 25)) a cssum r nor (r iso1 r iso2 r t2 ) (r nor r iso1 r iso2 r t2 ) r sum r drp (eq. 16) the typical equation of an ntc is based on a curve fit equation 17 rt2(t) rt2 25c e
1 273 t 1 298 (eq. 17) the demo board use a 10 k ntc with a value of 3740. figure 16 shows the comparison of the compensated output impedance and uncompensated output impedance varying with temperature. 0.0006 0.0007 0.0008 0.0009 0.001 0.0011 0.0012 0.0013 25 45 65 85 105 celsius ohm zout zout(uncomp) figure 16. z out vs. temperature imon for current monitor since vdrp signal reflects the current information of all phases. it can be fed into the imon amplifier for current monitoring as shown in figure 17. imon amplifier has a fixed gain of 2 with an offset when vdrp is equal to 1.3 v, the internal floating reference voltage. the imon amplifier will be saturated at an maximum output of 1.09 v therefore the total gain of current should be carefully considered to make the maximum load current indicated by the imon output. figure 18 shows a typical of the relation between imon output and the load current. + i1 i2 i3 i4 ilim acssum adrp ocp event + ? + ? riso1 riso2 rt2 rsum rnor + ? imon figure 17. imon circuit gain = 2 vimon vs. iout 0 0.21 0.42 0.63 0.84 1.05 0 102030405060708090100 iout ? a vimon ? v figure 18. imon output vs. output current power saving indicator (psi) and phase shedding vr11.1 requires the processor to provide an output signal to the vr controller to indicate when the processor is in a low power state. NCP5392 use the status of psi pin to decide if there is a need to change its operating state to maximize efficiency at light loads. when psi = 0, the psi function will be enabled, and vr system will be running at a single phase power saving mode. the psi signal will de ? assert 1 s prior to moving to a normal power state. at power saving mode, NCP5392 works with the ncp5359 driver to represent diode emulation mode at light load for further power saving. when system switches on psi function, an phase shedding will be presented. only one phase is active in the
NCP5392 http://onsemi.com 28 emulation mode while other phases are shed. figure 19 indicates a psi ? on transition from a 3 ? phase mode to a single phase mode. while staying stable in psi mode, the pwm signal of phase 1 will vary from a mid ? state level (1.5 v typical) to high level while other phases all go to mid ? state level. v ice verse, when psi signal goes high, the system will go back to the original phase mode such as shown in figure 20. figure 19. psi turns on, ch1: pwm1, ch2: pwm2, ch3: pwm3, ch4: psi figure 20. psi turns off, ch1: pwm1, ch2: pwm2, ch3: pwm3, ch4: psi vrhot thermal monitoring circuit consists of one sensitive comparator that compares the voltage on the ntc pin with an internal voltage reference. vr_hot is an open drain type of output. in normal temperature, the voltage value on ntc pin is higher than the internal reference, vr_hot will be low impedance. when the temperature is higher than certain threshold, the vr_hot will be high impedance. the following equations can be used to find the temperature trip points. rt1(t) rt1 25c e
1 273 t 1 298 (eq. 18) with a beta value of 3740, a 68 k ntc resistor is selected for rt1, rntc1 is populated with 19.6 k . vr_hot threshold is carefully selected to make sure when board temperature is less than 92 c. rntc1 rt1 0 + ? out 0.268 vcc vcc 0 ntc vrhot figure 21. vrhot circuit ovp improved performance the overvoltage protection threshold is not adjustable. ovp protection is enabled as soon as soft ? start begins and is disabled when part is disabled. when ovp is tripped, the controller commands all four gate drivers to enable their low side mosfets and vr_rdy transitions low. in order to recover from an ovp condition, v cc must fall below the uvlo threshold. see the state diagram for further details. the ovp circuit monitors the output of diffout. if the diffout signal reaches 180 mv (typical) above the nominal 1.3 v offset the ovp will trip and vrrdy will be pulled low, after eight consecutive ovp events are detected, all pwms will be latched. the diffout signal is the difference between the output voltage and the dac voltage (minus 19 mv if in vr11.1 modes) plus the 1.3 v internal offset. this results in the ovp tracking on the dac voltage even during a dynamic change in the vid setting during operation. figure 22. vr11.1, 1.6 v ovp event
NCP5392 http://onsemi.com 29 figure 23. amd, 1.55 v ovp event gate driver and mosfet selection on semiconductor provides the ncp5359 as a companion gate driver ic. the ncp5359 driver is optimized to work with a range of mosfets commonly used in cpu applications. the ncp5359 provides special functionality including power saving mode operation and is required for high performance dynamic vid operation. contact your local on semiconductor applications engineer for mosfet recommendations. board stackup and board layout close attention should be paid to the routing of the sense traces and control lines that propagate away from the controller ic. routing should follow the demo board example. for further information or layout review contact on semiconductor.
NCP5392 http://onsemi.com 30 system timing diagram figure 24. normal startup 500 s 500 s 3.5 ms vr_rdy vsp ? vsn vid drvon en uvlo 5 v (controller) 1.5 ms 1 s min valid vid 12 v (gate driver) uvlo figure 25. driver uvlo limited startup 500 s 500 s 3.5 ms vr_rdy vsp ? vsn vid drvon en uvlo 5 v (controller) por 1 ms 1.5 ms 1 s min uvlo valid vid 12 v (gate driver)
NCP5392 http://onsemi.com 31 figure 26. ovp shutdown 185 mv vsp = vid ? 19 mv drvon = high vr_rdy diffout ~ 1.3 v 185 mv 12345678 12345678 figure 27. non ? psi current limit vdrp vr_rdy drvon i limit + 1.3
NCP5392 http://onsemi.com 32 package dimensions qfn40 6x6, 0.5p case 488ar ? 01 issue a seating 40x k 0.15 c (a3) a a1 d2 b 1 11 20 21 40 2x 2x e2 40x 10 30 40x l 40x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 31 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 4.00 4.20 e 6.00 bsc 4.20 e2 4.00 e 0.50 bsc l 0.30 0.50 k 0.20 ??? 36x plane dimensions: millimeters 0.50 pitch 4.20 0.30 4.20 40x 36x 0.65 40x 6.30 6.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5392/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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